A NAND flash memory array includes rows and columns (strings) of cells. A cell may include a transistor. During a read operation, an entire row/page of the NAND flash memory array is read. This is done by applying a bias voltage to all rows not being read and a reference threshold voltage to the row that should be read.
The bias voltage allows the transistor of the NAND flash memory array to fully conduct. The cells lying on the row being read will conduct only if the threshold voltage is sufficiently high to overcome the trapped charge in the floating gate.
A sense amplifier is connected to each string which measures the current through the string and outputs either a “1” or a “0” depending whether the current passed a certain threshold.
Typically, a programming operation includes a process of multiple small charge injection steps. A charge may be injected to a cell by applying a voltage pulse (Vpulse), to the row being programmed and setting the gate voltages of all other transistors in the string to a bias voltage (Vbias).
After applying a voltage pulse, the programmed cell is read (using the procedure described above) and compared to the desired programming voltage. If the desired programming voltage is reached, the programming ends. Else, additional pulses are provided—until reaching the desired programming voltage or until reaching a maximal number of pulses (Nmaxpulses). If, after the maximal number of pulses is used, there remain cells that did not pass the verify test (were not programmed to the desired programming voltage), a program error (or failure) can be declared.
The programming process includes increasing the level of the voltage pulses (Vpulse) by a voltage increment known as Vstcp.
The programming parameters (e.g. Vbias, Vstep, Vstart, and Nmaxpulses) can be defined to provide a desired trade-off between speed and accuracy. Thus, higher Vstep and Vstart can assist in speeding up the programming process but may not be fitted to provide very narrow voltage threshold distribution lobes. Also, higher Nmaxpulses will reduce the chances of programming failures while lower Nmaxpulses shorten the programming process.
The above described programming procedure may be applied when programming a single bit per cell, or two or more bits per cell. If a single bit per cell is programmed, the programming pulses would typically be applied only to strings with corresponding data bits equal to zero.
In a multi-level Flash device pages are separated by n-levels, corresponding to the number of bits stored per cell.
A three bits per cell flash memory array can be programmed to store Most Significant Bit (MSB) pages, Central Significant Bit (CSB) pages and Least Significant Bit (LSB) cells.
FIG. 1 illustrates eight voltage threshold distribution lobes (lobes) 11-18, starting from an erase lobe (the leftmost lobe) and ending at the highest value lobe 18. FIG. 1 also illustrates a MSB read threshold 24 (positioned between the fourth and fifth lobes), two CSB read thresholds 22 and 26 and four LSB read thresholds 21, 23, 25 and 27.
As may be noticed from FIG. 1, for reading an MSB page, only a single threshold comparison (to MSB read threshold 24) should be performed. For reading a CSB page, two CSB read thresholds 22 and 26 are to be used in order to determine the bit value of every CSB associated cell. For LSB pages the bit-values are determined using the four LSB read thresholds 21, 23, 25 and 27.
An MSB page is read by using the MSB read threshold 24. All threshold voltages that belong to lobes (15-18) above the MSB read threshold 24 will be read as “0”s and all threshold voltages that belong to lobes (11-14) below the MSB read threshold 24 will be read as “1”s.
A CSB page is read by using two CSB read thresholds 22 and 26. All threshold voltages that belong to lobes (11 and 12) below the first CSB read threshold 22 and all threshold voltages that belong to lobes above (17 and 18) the second CSB read threshold 26 level will be read as “1”s. All threshold voltages that belong to lobes (13-16) between the two CSB read thresholds 22 and 26 will be read as “0”s. Similarly, the LSB pages are read by applying four LSB thresholds 21, 23, 25 and 27.
The lobes of FIG. 1 are non-overlapping, however this is only schematic, and in practical cases the lobes may overlap. The overlapping can be intentional (for obtaining higher programming speed), or due to the retention effect.
The programming and erasing of flash memory cells cause unwanted charges to be trapped in the flash memory cells. These charges can introduce errors in the programming and reading processes.
After long periods or after multiple program and erase cycles the lobes tend to widen, to move to the left (towards lower voltage threshold levels) and in many cases to overlap due to trap charge leakage. This phenomenon is also known as detrapping or retention effect. Flash memory cells that are more affected by the retention effect can be considered as being worn. The wear level of a cell can be at least partially reduced due to trap charge discharge.
Due to the retention, the read thresholds should change over time in order to at least partially compensate for the change in the lobes' distribution.